A fast transistor-chaining algorithm for CMOS cell layout

We propose a fast algorithm for the transistor-chaining problem in CMOS functional cell layout based on Uehara and van Manuscript received January 4, 1989; revised May 31, 1989. This work was supported in part by ERSO under Contract SF-C-010-1 and by the Cleemput’s layout style [lZ]. Our algorithm takes a transistor-level circuit schematic and outputs a minimum set of transistor chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the set of branches needed to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables us to prune the search tree efficiently. The algorithm has been implemented and tested. It is able to find optimal solutions almost instantly for all the cases available to us from the literature. Keywords-CMOS cell layout, optimal chaining, transistor placement, depth-first search.